The present application relates to power semiconductor devices, methods, and circuits, and more particularly to power semiconductor devices, methods, and circuits which make use of permanent or immobile electrostatic charge.
Note that the points discussed below may reflect the hindsight gained from the disclosed inventions, and are not necessarily admitted to be prior art.
Power MOSFETs are widely used as switching devices in many electronic applications. In order to minimize the conduction power loss it is desirable that power MOSFETs have a low specific on-resistance (RSP or R*A), which is defined as the product of the on-resistance of the MOSFET multiplied by the active die area. In general, the on-resistance of a power MOSFET is dominated by the channel resistance and the drift region resistances which include the channel resistance, spreading resistance and the epitaxial layer resistance. Recently, the so called superjunction structure has been developed to reduce the drift region resistance. The superjunction is constructed by paralleling highly doped alternating p-type and n-type layers or pillars. The doping concentrations of n-type pillar (the n-type drift region), for the same breakdown voltage, can be significantly higher than that of conventional drift region provided that the total charge of n-type pillar is designed to be balanced with charge in the p-type pillar. In order to fully realize the merit of the superjunction, it is desirable to pack many pillars in a given area to achieve a lower RSP. However, the minimum widths, which can be reached in device manufacturing, of the n-type and p-type pillars set a limitation on the cell pitch that can be achieved and the resulting device size.
With reference to FIG. 1, a cross-sectional structural diagram depicts a power MOSFET design as shown in other patent applications which are commonly owned. (See the list of applications given below, which all have at least overlapping ownership, inventorship and copendency with the present application, and all of which are hereby incorporated by reference.) Note that these applications are not necessarily prior art to the present application. This device includes a drain region 102, e.g. a substrate, underlying a p-type drift region 104, which may be provided by an epitaxial layer. A p-body region 106 (contacted by a p+ body contact region 110) separates a source region 108 from the drift region 104. A trench is largely filled with dielectric material 114, but also contains a gate electrode 112. Gate electrode 112 is capacitively coupled to nearby portions of body 106, so that, depending on the applied gate voltage, an inversion layer may be formed at the surface of the body region 106, creating a channel. Frontside source metallization 101 makes ohmic contact to source and body, and backside drain metallization 103 makes ohmic contact to the drain diffusion 102.
Another very important feature is that the device incorporates a sheet of fixed or permanent positive charge (QF) 116, at or near the sidewalls of the trench, which balances the charge of p-type in the off state. The permanent charge 116 also forms a electron drift region in a power MOSFET by forming an inversion layer along the interface between the dielectric material 114 (e.g. oxide) and P Epi layer 104. By making use of this new concept, the scaling limitation due to inter-diffusion of p-type pillar and n-type pillar can be reduced. Consequently, a small cell pitch and high pillar packing density can be realized to reduce the device total on-resistance and RSP.
However, as the cell pitch is reduced the intrinsic capacitances of the device, such as gate-to-source capacitance (Cgs) and gate-to-drain capacitance (Cgd), also increase. As a consequence, the switching loss of the device increases. This is undesirable.
The turn-on characteristics of the device in FIG. 1 have been simulated. The key components of device capacitances during the device turn-on process are illustrated by the internal electric field lines shown in FIG. 2. The most significant component which controls the device switching, power losses, is the total charge associated with charging or discharging the gate-drain capacitance Cgd. This charge is the so-called “Miller charge” Qgd. Therefore, it is important to reduce Qgd in order to reduce total losses.